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Seeing through hardware counters: a journey to threefold performance increase

The Netflix TechBlog

We also see much higher L1 cache activity combined with 4x higher count of MACHINE_CLEARS. a usage pattern occurring when 2 cores reading from / writing to unrelated variables that happen to share the same L1 cache line. Cache line is a concept similar to memory page?—? Thread 0’s cache in this example.

Hardware 363
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Predictive CPU isolation of containers at Netflix

The Netflix TechBlog

Because microprocessors are so fast, computer architecture design has evolved towards adding various levels of caching between compute units and the main memory, in order to hide the latency of bringing the bits to the brains. This avoids thrashing caches too much for B and evens out the pressure on the L3 caches of the machine.

Cache 255
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Compress objects, not cache lines: an object-based compressed memory hierarchy

The Morning Paper

Compress objects, not cache lines: an object-based compressed memory hierarchy Tsai & Sanchez, ASPLOS’19. Existing cache and main memory compression techniques compress data in small fixed-size blocks, typically cache lines. Hotpads is a hardware-managed hierarchy of scratchpad-like memories called pads.

Cache 61
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From Heavy Metal to Irrational Exuberance

ACM Sigarch

These, let’s call them metal languages , include FORTRAN (introduced in 1957), C (1972), and C++ (1985). Programmers continue to write applications in them, and they continue to evolve: the just approved C++20 standard is the latest example. Are caches large enough for this code? As Leiserson et al.

C++ 108
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Distributed Algorithms in NoSQL Databases

Highly Scalable

A database should accommodate itself to different data distributions, cluster topologies and hardware configurations. C) In the previous schema, failures can be handled better using the hinted handoff technique [8]. Consider an example: there are 3 nodes A, B, and C and increment operation was applied 3 times, once per node.

Database 213
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WiredTiger Logging and Checkpoint Mechanism

Percona

” This acts as a step to ensure durability by recovering lost data from the same journal files in case of crashes, power, and hardware failures between the checkpoints (see below) Here’s what the process looks like. The same data, in the form of pages inside the Wiredtiger cache, are also marked dirty. wt and index-*.wt).

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This spring: High-Performance and Low-Latency C++ (Stockholm) and ACCU (Bristol)

Sutter's Mill

I don’t get to Europe very often apart from ISO C++ standards meetings, but this spring I’ve been able to accept invitations for two English-language European events in the last week of April. Tue-Thu Apr 25-27: High-Performance and Low-Latency C++ (Stockholm).

Latency 48