Dynatrace

JUNE 27, 2022

In some cases, you will lack benchmarking capabilities. connectivity, access, user count, latency) of geographic regions. Because pre-production environments are used for testing before an application is released to end users, teams have no access to real-user data. RUM generates a lot of data. Synthetic monitoring drawbacks.

Best Practices 244

Best Practices Monitoring Wireless Traffic 244

Brendan Gregg

JUNE 30, 2018

These have inspired me to summarize another performance activity: evaluating benchmark accuracy. Accurate benchmarking rewards engineering investment that actually improves performance, but, unfortunately, inaccurate benchmarking is more common. If the benchmark reported 20k ops/sec, you should ask: why not 40k ops/sec?

Benchmarking 47

Benchmarking Latency Cache Network 47

Brendan Gregg

JUNE 29, 2018

These have inspired me to summarize another performance activity: evaluating benchmark accuracy. Accurate benchmarking rewards engineering investment that actually improves performance, but, unfortunately, inaccurate benchmarking is more common. If the benchmark reported 20k ops/sec, you should ask: why not 40k ops/sec?

Benchmarking 40

Benchmarking Latency Cache Network 40

CSS - Tricks

APRIL 1, 2021

Google’s industry benchmarks from 2018 also provide a striking breakdown of how each second of loading affects bounce rates. With all of this in mind, I thought improving the speed of my own version of a slow site would be a fun exercise. billion if the site slowed down by just one second. Source: Google /SOASTA Research, 2018.

Cache 94

Cache Social Media Media Website 94

John McCalpin

JANUARY 22, 2018

The exercise seemed simple enough — just fix one item in the Colfax code and we should be finished. Each of the two vector units can issue one FMA instruction per cycle, assuming that there are enough independent accumulators to tolerate the 6-cycle dependent-operation latency. Instead, we found puzzle after puzzle.

Latency 40

Latency Hardware Code Testing 40

John McCalpin

JANUARY 22, 2018

There was no deep goal — just a desire to see the maximum GFLOPS in action. The exercise seemed simple enough — just fix one item in the Colfax code and we should be finished. Using the minimum number of accumulator registers needed to tolerate the pipeline latency (12), the assembly code for the inner loop is: B1.8:

Latency 40

Latency Hardware Code Testing 40