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Distance-Based ISA for Efficient Register Management

ACM Sigarch

To create a CPU core that can execute a large number of instructions in parallel, it is necessary to improve both the architecturewhich includes the overall CPU design and the instruction set architecture (ISA) designand the microarchitecture, which refers to the hardware design that optimizes instruction execution.

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Impact of Querying Table Information From information_schema

Percona

Disclaimer : This blog post is meant to show a less-known problem but is not meant to be a serious benchmark. The percentage in degradation will vary depending on many factors {hardware, workload, number of tables, configuration, etc.}. Setup The setup consists of creating 10K tables with sysbench and adding 20 FKs to 20 tables.

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Compress objects, not cache lines: an object-based compressed memory hierarchy

The Morning Paper

Compress objects, not cache lines: an object-based compressed memory hierarchy Tsai & Sanchez, ASPLOS’19. Existing cache and main memory compression techniques compress data in small fixed-size blocks, typically cache lines. Hotpads is a hardware-managed hierarchy of scratchpad-like memories called pads.

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Crucial Redis Monitoring Metrics You Must Watch

Scalegrid

Key metrics like throughput, request latency, and memory utilization are essential for assessing Redis health, with tools like the MONITOR command and Redis-benchmark for latency and throughput analysis and MEMORY USAGE/STATS commands for evaluating memory. Cache Hit Ratio The cache hit ratio represents the efficiency of cache usage.

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InnoDB Performance Optimization Basics

Percona

Hardware Memory The amount of RAM to be provisioned for database servers can vary greatly depending on the size of the database and the specific requirements of the company. By caching hot datasets, indexes, and ongoing changes, InnoDB can provide faster response times and utilize disk IO in a much more optimal way. I hope this helps!

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The Return of the Frame Pointers

Brendan Gregg

Only in extreme circumstances does the cost (in processor time and I-cache footprint) translate to a tangible benefit - circumstances which usually resort to hand-coded assembly anyway. It shouldn't be 10%, unless it's cache effects. And for leaf routines (which never establish a frame), this is a non-issue.

Java 137
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The evolution of single-core bandwidth in multicore processors

John McCalpin

For most high-end processors these values have remained in the range of 75% to 85% of the peak DRAM bandwidth of the system over the past 15-20 years — an amazing accomplishment given the increase in core count (with its associated cache coherence issues), number of DRAM channels, and ever-increasing pipelining of the DRAMs themselves.